High impedance signal conversion circuit and method

ABSTRACT

A circuit (200) comprises transistors (240, 250, 260), an operational amplifier (270) and serially coupled resistors (210, 220). The circuit (200) is coupled to reference lines (201, 202). An input voltage V X  on an input terminal (203) is applied across the resistors (210, 220) and divided to an output voltage V Y  on an output terminal (204). Output voltage V Y  is measured (as V M ) by the operational amplifier (270). The operational amplifier (270) controls a current I A  in a first current path between the reference lines (201, 202). The current I A  is mirrored to a current I S  in a second current path through the resistors (210, 220). The current I S  is generated by one of the transistors (260) and substantially proportional to the input voltage V X . Therefore, the resistors (210, 220) do not substantially load the input and the circuit (200) exhibits a high input impedance.

FIELD OF THE INVENTION

The present invention generally relates to electronic circuits, and, more particularly to a circuit for converting voltages.

BACKGROUND OF THE INVENTION

In modern technologies, electronic devices, such as computers, printers, scanners, modems, are getting more and more compatible and interchangeable. Also, supply voltages for such devices are decreasing.

FIG. 1 is a simplified block diagram of a prior art arrangement of device 10 with supply voltage V_(S1) (e.g., so-called rail-to-rail voltage) and device 20 having supply voltage V_(S2) ≦V_(S1). Convenient examples for the voltages are V_(S1) =5 volts and V_(S2) =3.3 volts. Device 10 may send signals 15 having temporarily a voltage V₁ <V_(S1) to device 20. Second device 20 must accommodate V_(S1). Device 20 receives signal 15 by voltage divider 30 serving as a signal conversion circuit. Voltage divider 30 has resistors 31 and 32 serially coupled to common reference 35 of circuits 10 and 20. With magnitudes R_(A) and R_(B) of resistors 31 and 32, respectively, voltage divider 30 provides an intermediate voltage V₂ : ##EQU1## Voltage divider 30 consumes a current I: ##EQU2## Such a current leads to power consumption in device 10 which is not convenient. In other words, circuit 10 must have enough drive capability to accommodate a low input impedance of the conversion circuit (e.g., voltage divider 30) in device 20. The impedance of circuit 20 should be high, not low. A configuration as in FIG. 1 is especially inconvenient when circuit 10 is a battery powered interface whose battery is discharged by current I.

The present invention seeks to provide an improved signal conversion circuit which mitigates or avoid the above mentioned and other disadvantages and limitations of the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a simplified block diagram of a prior art arrangement of a first circuit with a first supply voltage and a second circuit with a second supply voltage;

FIG. 2 illustrates a simplified block diagram of a circuit of the present invention;

FIG. 3 illustrates a simplified circuit diagram of a circuit in a first embodiment of the present invention; and

FIG. 4 illustrates a simplified circuit diagram of a circuit in a second embodiment of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 2 illustrates a simplified block diagram of signal conversion circuit 100 (hereinafter circuit 100) of the present invention. Circuit 100 comprises variable current source 150, network 110 of elements 115 and control unit 130. Preferably, elements 115 of network 110 are serially coupled. Network 110 has an impedance Z. Impedance Z is intended to include ohmic resistors R, capacities C, inductances L and combinations thereof. Network 110 receives input voltage V_(X) and provides measurement voltage V_(M) and output voltage V_(Y). Preferably, the voltages are related as:

    V.sub.M =b*V.sub.X                                         (3)

    V.sub.Y =a*V.sub.X                                         (4)

with factors a and b being complex numbers. Preferably, a and b are real numbers between 0 and 1. Conveniently, network 110 has at least two elements 115 in a voltage divider configuration. But this is not essential.

Current source 150 generates current I_(S). Control unit 130 receives measurement voltage V_(M) and controls current source 150 such that:

    I.sub.S =V.sub.X /Z                                        (5)

with the fraction line for division. In other words, the current I_(S) through network 110 follows a fraction (e.g., V_(M)) of the input voltage V_(X). Control unit 130 is conveniently an amplifier which does not require the full swing of V_(X), but accommodates the smaller swing of voltage V_(M). Conveniently, impedance Z is substantially independent from input voltage V_(X).

Before explaining details of the present invention in connection with FIG. 3, conventions used herein are explained. The term "transistor" is intended to include any device having at least two main electrodes and a control electrode. The impedance between the main elements is controlled by a signal applied to the control electrode. The transistors used to implement the present invention are, preferably, field effect transistors (FET) having source (S) and drain (D) as main electrodes and a gate (G) as control electrode. For convenience, the abbreviations also appear in the figures. Since FET are typically symmetrical components, the true designation of "source" and "drain" is only possible once a voltage is impressed on the terminals. The designation of sources (S) and drains (D) herein should therefore be interpreted in the broadest sense. Transistors can also be bipolar transistors with, for example, collectors and emitters as main electrodes and bases as control electrodes, or other devices. The present invention is useful but not limited to CMOS-technology using P-channel FET ("P-FET") and N-channel FET ("N-FET"). The terms "first type" (e.g., for P-FET 260) and "second type" (e.g., for N-FET 240) are intended to distinguish complementary transistors of opposite conductivity. For convenience, FIG. 3 illustrate the gates (G) of P-FET by small circles.

FIG. 3 illustrates a simplified circuit diagram of circuit 200 in a preferred embodiment of the present invention. Circuit 200 is based on circuit 100 of FIG. 2. Circuit 200 comprises resistors 210, 220 and 230, transistors 240, 250 and 260, and operational amplifier (op amp) 270. Transistors 250 and 260 are preferably, P-FETs and transistor 240 is an N-FET. Circuits 200 receives a supply voltage V_(S) between reference lines 201 and 202. Circuit 200 receives an input voltage V_(X) at input terminal 203 and provides an output voltage V_(Y) at output terminal 204. For convenience, voltages are referred to line 202. Transistors 250 and 260 form current mirror 265 (dashed frame). Resistors 210 and 220 form voltage divider 215 (dashed frame). Transistor 250 has the function of a variable current source 150.

The source (S) of transistor 260 is coupled to line 201. The drain (D) of transistor 260 is coupled to resistor 210 at node 205. Resistor 210 is serially coupled to line 202 via node 206 and resistor 220. Input terminal 203 is coupled to node 205; and output terminal 204 is coupled to node 206. Node 206 is coupled to non-inverting input 271 of op amp 270. Inverting input 272 of op amp 270 is coupled to the source (S) of transistor 240 and coupled to line 202 via resistor 230. Output 273 of op amp 270 is coupled to the gate (G) of transistor 240. The drain (D) of transistor 240 is coupled to the drain (D) and to the gate (G) of transistor 250 and to the gate (G) of transistor 260. The source (S) of transistor 250 is coupled to line 201.

Resistors 210, 220, and 230 have resistance magnitudes R₁, R₂, and R₃, respectively. The source-drain path of transistor 260 provides current I_(S) which flows into node 205. Input current I_(X) also flows into node 205 and is combined with current I_(S) to provide current I_(R) trough resistors 210 and 220:

    I.sub.R =I.sub.S +I.sub.X                                  (6)

Equation (6) is the application of Kirchhoff's Node Law. For convenience of explanation, the currents from node 206 to output terminal 204 and to input 271 of op amp 270 are neglected. Input voltage V_(X) appears across resistors 210 and 220 between nodes 205 and line 202. Output voltage V_(Y) and measurement voltage V_(M) appear across resistor 220 between node 206 and line 202. In the example of FIG. 3, output voltage and measurement voltage are substantially equal (≈):

    V.sub.Y ≈V.sub.M (i.e., a≈b)               (7)

Voltages V_(M) depends on input voltage V_(X) and the values R₁ of resistor 210 and R₂ of resistors 220 according to the well known relation for voltage dividers: ##EQU3## with the symbol * for multiplication. The source-drain paths of transistors 240 and 250 carry current I_(A) conveniently defined in the direction from line 201 to line 202. Op amp 270, resistor 230 and transistor 240 form a voltage controlled current source. Current I_(A) is related to V_(M) trough the magnitude R₃ of resistor 230:

    I.sub.A =V.sub.M /R.sub.3                                  (9)

Transistors 250 and 260 of current mirror 265 provide current I_(S) by scaling current I_(A) with a substantially proportional factor k:

    I.sub.S =k*I.sub.A                                         (10)

Factor k is a real number and related to the magnitudes R₃ and R₂ as:

    k=R.sub.3 /R.sub.2                                         (11)

Preferably, the magnitudes of resistors 220 and 230 are substantially equal (≈):

    R.sub.2 ≈R.sub.3                                   (12)

so that factor k is about k≈1. But other values can also be used.

Assume that transistor 260 is disconnected from circuit 200 and input voltage V_(X) causes current I_(R) through resistors 210 and 220 according to: ##EQU4## Such an arrangement would have low impedance and would take energy from input terminal 203. According to the invention, current I_(R) is substantially provided by variable currents source 150 (e.g., transistor 260):

    I.sub.R ≈I.sub.S                                   (14)

I_(X) can be neglected and assumed to be around zero:

    I.sub.X ≈0                                         (15)

Changes in the magnitude of I_(S) are controlled according to changes in the magnitude of input voltage V_(X). Using equations (8), (9), and (10), I_(S) is calculated as: ##EQU5## It is also convenient when currents I_(S) and I_(A) are also substantially equal:

    I.sub.S ≈I.sub.A (i.e., k≈1)               (18)

Resistors 210 and 220 are, conveniently related as:

    R.sub.2 =r*R.sub.1                                         (19)

Factor r is conveniently a real number from almost zero (r≈0) to r≈10 or higher. Preferably, factor r has a value of about:

    0.05≈<r≈<1                                 (20)

It is an important advantage of the present invention that circuit 200 can be used in modern low voltage applications. For convenience, voltages are considered as absolute values ||. The supply voltage |V_(S) | is larger to or substantially equal (≧) to the sum of the drain-source voltage |V_(DS) | of transistor 260 (line 201 and node 205) and input voltage V_(X) (node 205 to line 202):

    |V.sub.S |≧|V.sub.DS |+|V.sub.X |                   (21)

Transistor 260 preferably operates in the saturation region so that the voltage |V_(DS) | is a saturation ("SAT") voltage |V_(DSAT) |. Input voltage V_(X) can be expressed by R₁, R₂, and I_(S). Supply voltage |V_(S) | can also be estimated as:

    |V.sub.S |≧|V.sub.DSAT |+{(R.sub.1 +R.sub.2)*I.sub.S }                  (22)

When circuit 200 is implemented on a monolithic chip with a CMOS-process, supply voltage |V_(S) | can be as low as, for example and not intended to be limiting 1.8 volts.

Circuit 200 of the present invention is compared to resistor arrangement 31/32 in device 20 of the prior art. By simulation, similar sine signals are applied as input signals and the input currents are measured. The simulation method is SPICE, but other simulation methods well known in the art would lead to similar results. Resistance magnitude are, for example,

    R.sub.A =R.sub.1 =10 kΩ (resistors 31 and 210, respectively) (23)

    R.sub.B =R.sub.2 =10 kΩ (resistors 32 and 220, respectively) (24)

(a) First, a voltage V₁ was applied across resistors 31 and 32 (cf. FIG. 1) of prior art circuit 20. In a well known representation, voltage V₁ is expressed as:

    V.sub.1 =V.sub.DC +V.sub.AC *sin(2*π*F*t)               (25)

with frequency F, time t, π≈3.14 . . . , and "sin" for the sine function. The usual abbreviations "DC" and "AC" stand for "direct current" and for "alternating current", respectively. The frequency was F≈5 MHz. A resulting current I, similarly expressed as:

    I=I.sub.DC +I.sub.AC *sin(2*π*F*t)                      (26)

was determined with I_(DC) ≈100 μA and I_(AC) ≈5 μA.

(b) Second, a similar voltage V_(X) ≈V₁ with the same frequency F was applied to circuit 200 of the present invention. A resulting current I_(X) was determined with I_(DC) '≈2 μA and I_(AC) '≈1 μA. Circuit 200 has input current I_(X) which is about 5 times (for AC) and 50 times (for DC) lower than input current I of prior art arrangement 31/32. In other words, circuit 200 has a high input impedance and does not significantly load the source of I_(X).

FIG. 4 illustrates a simplified circuit diagram of circuit 200' in a second embodiment of the present invention. Circuit 200' is a variation of circuit 200 (FIG. 3) without optional transistor 240. Primed reference numbers in FIG. 4 correspond to unprimed numbers in FIG. 3. For simplicity, voltages and currents are not illustrated in FIG. 4. Circuit 200' comprises transistors 250' and 260', resistors 210', 220', and 230' and op amp 270'. Transistors 250' and 260' are, preferably, P-FETs. Circuit 200' has a first current path from line 201 to line 202 with serially coupled source (S) and drain (D) of transistor 260', node 205', resistor 210', node 206', and resistor 220'.

Circuit 200' has a second current path with the source (S) of transistor 250' coupled to line 201', the drain (D) of transistor 250' coupled to line 202' via resistor 230'. Output 273' of op amp 270' is coupled to the gates (G) of transistors 250' and 260'. Non-inverting input 271' of op amp 270 is coupled to the drain (D) of transistor 250'. Inverting input 272' of op amp 270 is coupled to node 206'.

The operation of circuit 100 and its embodiments in circuits 200 and 200' can be described as a method of the present invention. The method provides a substantially constant impedance between a first node (e.g., node 205) and a second node (e.g., line 202) which receive a voltage V_(X). The method comprises the following steps:

(1) A partial voltage V_(M) is measured between reference points located between the nodes. The reference points are, for example, node 206 and line 202 (FIG. 3). One of the reference points can be obtained, for example, by a resistor voltage divider (e.g., resistors 210 and 220) between the nodes.

(2) A current I_(S) is provided to the first node. The current I_(S) has a variable magnitude which corresponds to a magnitude of a current I_(X) which is caused by V_(X) across a resistance (e.g., R₁ +R₂) between the nodes. Current I_(S) can be provided by converting the partial voltage V_(M) to a current I_(A) (e.g., in op amp 270) and mirroring the current I_(A) (by e.g., transistors 250 and 260).

While the invention has been described in terms of particular structures, devices and methods, those of skill in the art will understand based on the description herein that it is not limited merely to such examples and that the full scope of the invention is properly determined by the claims that follow. 

We claim:
 1. A circuit, comprising:(a) a first resistor and a second resistor serially coupled forreceiving a variable input voltage V_(X) across said first and second resistors and providing an output voltage V_(Y) across said second resistor; (b) a variable current source serially coupled to said first and second resistors via a first node, for supplying a variable current I_(S) to said first node; (c) a control unit coupled to said first and second resistors for measuring a voltage V_(M) at a second node between said first and second resistors and controlling said variable current source such that said variable current I_(S) supplied to said first and second resistors is proportional to said variable input voltage V_(X).
 2. The circuit of claim 1 wherein said current source is a current mirror which receives a current I_(A) from said control unit and provides I_(S) =k*I_(A) with a k being a substantially proportional factor.
 3. The circuit of claim 2 wherein k≈1.
 4. The circuit of claim 1 wherein said voltage V_(M) is substantially equal to a voltage across said second resistor.
 5. The circuit of claim 1 wherein magnitudes R₁ and R₂ of said first and second resistors, respectively, are related by R₂ =r*R₁ with 0.05≈<r≈<1.
 6. The circuit of claim 1 wherein said control unit has an output coupled to said variable current source through a current mirror.
 7. The circuit of claim 6 whereinsaid output is coupled to a reference line by a third resistor, said second resistor is coupled between said node and said reference line, and said second and third resistors have substantially equal magnitudes.
 8. A method for providing a substantially constant impedance between a first node and a second node receiving a voltage V_(X), comprising the steps of:(1) measuring a partial voltage V_(M) between first and second reference points located between said first node and said second node; and (2) providing a current I_(S) to said first node, said current I_(S) having a variable magnitude corresponding to a magnitude of a current I_(X) which is caused by V_(X) across a resistance between said first and second nodes.
 9. The method of claim 8 wherein said first reference point is obtained by a resistor voltage divider between said first and second nodes.
 10. The method of claim 8 wherein said current I_(S) is provided by the steps of(a) converting said partial voltage V_(M) to a current I_(A) and (b) mirroring said current I_(A) to provide current I_(S).
 11. A high impedance signal conversion circuit receiving an input voltage V_(X) and providing an output voltage V_(Y) ≦V_(X),said circuit comprising: a network of at least two elements,said network receiving said input voltage V_(X) and providing(1) said output voltage V_(Y) =a*V_(X) and (2) a measurement voltage V_(M) =b*V_(X), said network having a total impedance Z; a first transistor having main electrodes serially coupled to said network for providing a current I_(S) to said network; and an amplifier receiving said measurement voltage V_(M) and controlling a control electrode of said first transistor, such that said current I_(S) is V_(X) /Z.
 12. The circuit of claim 11 wherein a≈b.
 13. The circuit of claim 11 wherein said elements of said network are resistors.
 14. The circuit of claim 11 wherein said elements of said network are a first resistor and a second resistor.
 15. The circuit of claim 11 wherein said elements of said network are serially coupled.
 16. The circuit of claim 11 whereinsaid amplifier is an operational amplifier having(a) a first input receiving said measurement voltage V_(M) ; (b) a second input receiving a reference voltage V_(M) ; and (c) an output coupled to said control electrode.
 17. The circuit of claim 16 wherein said output of said operational amplifier is coupled to a reference line by a resistor.
 18. The circuit of claim 11 wherein(a) said network has a first resistor with a magnitude R₁ and a second resistor with a magnitude R₂, (b) said second resistor provides said measurement voltage V_(M), (c) said amplifier comprises (i) a differential amplifier with a non-inverting input coupled to said second resistor, an inverting input, and an output, (ii) a third resistor being coupled to said inverting input, and (iii) a second transistor having a control electrode coupled to said output and a main electrode coupled to said third resistor for providing an intermediate current I_(A), a first main electrode coupled to said third resistor, and a second main electrode, and (d) a fourth transistor mirrors said intermediate current I_(A) to said current I_(S) =k*I_(A). 